
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   23:43:34 12/03/2008
-- Design Name:   key_reader
-- Module Name:   E:/Xilinx/Projects/ISE 9.2/keyboard_interface/key_reader_tb.vhd
-- Project Name:  keyboard_interface
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: key_reader
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY key_reader_tb_vhd IS
END key_reader_tb_vhd;

ARCHITECTURE behavior OF key_reader_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT key_reader
	PORT(
		ClkIn : IN std_logic;
		Reset : IN std_logic;
		KBD_CLOCK : IN std_logic;
		KBD_DATA : IN std_logic;          
		key_data : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL ClkIn :  std_logic := '0';
	SIGNAL Reset :  std_logic := '0';
	SIGNAL KBD_CLOCK :  std_logic := '0';
	SIGNAL KBD_DATA :  std_logic := '1';				--active low

	--Outputs
	SIGNAL key_data :  std_logic_vector(7 downto 0);

	--signals
	
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: key_reader PORT MAP(
		ClkIn => ClkIn,
		Reset => Reset,
		KBD_CLOCK => KBD_CLOCK,
		KBD_DATA => KBD_DATA,
		key_data => key_data
	);

	clocking: process
	begin
		KBD_CLOCK <= '0';
		wait for 5 ns;
		KBD_CLOCK <= '1';
		wait for 5 ns;
	end process;
	
	send_keys: process
	begin
		wait for 25 ns;
		KBD_DATA <= '0';	--start bit
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '1';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '1';
		wait for 10 ns;
		KBD_DATA <= '1';	--parity
		wait for 10 ns;
		KBD_DATA <= '1';	--stop bit
		wait for 20 ns;
		
		KBD_DATA <= '0';	--start bit
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '1';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '0';
		wait for 10 ns;
		KBD_DATA <= '1';
		wait for 10 ns;
		KBD_DATA <= '0';	--ERROR IN parity
		wait for 10 ns;
		KBD_DATA <= '1';	--stop bit
		wait;
	end process;
	
	
END;
